EPEPS 2024: 33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems Schwartz Reisman Innovation Campus Toronto, Canada, October 6-9, 2024

EPEPS is the premier international conference on advanced and emerging issues in the electrical modeling, analysis, and design of electronic interconnections, packages, and systems.  Over four days, the conference will feature the latest advancements in modeling, design, and measurement techniques for:

• signal integrity & power integrity
• advanced packaging and heterogeneous integration
• performance optimization 

of systems for high-speed electronics, RF and wireless communication, and quantum computing.

We look forward to seeing you in Toronto!

Piero Triverio & Wendem Beyene

Highlights & reasons to attend

• top-notch 4-day program, with keynotes, presentations, posters and demo sessions focused on the latest advancements from academia and industry
• four prestigious awards for the best contributions
• a full day of tutorials on the latest advancements in package/PCB design, signal and power integrity modeling, high-speed SerDes simulation, high precision measurement techniques and novel interconnect designs
• IEEE education credits: attend EPEPS and earn professional development hours (PDHs) and continuing education units (CEUs)
• industry exhibition and demos, to learn about the latest products and solutions available on the market
• sponsorship & exhibitor opportunities to promote your company's latest developments and increase your brand visibility to a specialized audience from the top companies and universities in the field
• Toronto is the fastest growing tech hub in North America, home of a talent pool of 400,000+ post-secondary students, and one of the most vibrant and multicultural cities in the world
• visit Canada in its most spectacular season, with Fall colors in full swing and the Niagara Falls only 1.5 hours away!

Call for papers

We welcome new and unpublished contributions in the following areas:

Interconnects design & technologies

• High-speed channels, backplanes, SerDes, memory, DDR interfaces
• Interconnect and transceiver co-design, equalization
• Signal & power integrity issues
• Jitter, noise
• High-frequency interconnects, packages, antennas-in-package
• Novel/unconventional interconnect technologies

Packaging and integration

• Advanced packaging, 3D integration
• Heterogeneous integration
• Design of interconnects and packages
• Quantum systems: interconnection & packaging aspects

Manufacturing and measurement

• Manufacturing, testing, reliability
• Measurement techniques

Modeling and simulation

• Modeling, simulation, computer-aided design
• Thermal, mechanical, multiphysics modeling
• ML and AI-based approaches to interconnect and packaging problems

Important dates

• Paper submission:  June 14, 2024 (see template and instructions here)
• Acceptance:  End of July 2024
• Sponsor registration:  August 6th, 2024
• Early bird registration:  September 6th, 2024

Organizing committee

• General chair: Prof. Piero Triverio, University of Toronto
• Co-chair: Dr. Wendem Beyene, Meta
• Finance chair: Dr. Vaishnav Srinivas, Qualcomm
• Website chair: Prof. Xu Chen, University of Illinos at Urbana-Champaign