Download PDFOpen PDF in browserOpen Defect Fault Analysis in Single Cell SRAM Using R, and C Parasitic Extraction MethodEasyChair Preprint 51324 pages•Date: March 12, 2021AbstractAs the technology changes from Submicron to Very Deep Sub Micron (VDSM) it is very difficult to test the SRAM on SOC. This allowing the huge integration dense causes the unwanted interconnections and disjunctions. This may create several defects in the memory layout which causes several memory faults within the cell. From the past literature, it is observed that many of the fault models are analyzed using several March algorithms such as March C to March 22N. These algorithms are predominant in detection information rather than location. As the technology scaling is increasing, the device density is more prone to parasitic effects that lead to some form of undetectable faults. However the existing test methods are not adequate to identify such undetectable faults. In this paper we propose a new fault model taking parasitic effects into consideration, to detect the faults along with fault location. The proposed method in this paper is considered node-to -node open defects at the circuit level using 120nm technology. Test results observed with few existing faults like Undefined Sate Faults (USF), Transition Faults (TF), Undefined Read Faults (URF), Undefined Write Faults (UWF), Incorrect Read Faults (IRF), Incorrect Write Faults (IWF) and No Access Faults (NAF). In addition to these, few more undetectable faults also observed at the locations of transistor M1 drain to node Q. These faults can easily be identified using proposed parasitic extraction method with observed R value of 3.7 kΩ and C value of 4.7fF. Similarly, other undetectable faults observed at nodes M2 drain and Q with corresponding R value of 4.14kΩ and C value of 5.1fF. Other one more fault undetectable fault observed at gate of M2 and node QB with correspond R value at node QB is 3.73kΩ and C is 6.49fF. Keyphrases: Deep submicron technology, March algorithm, Open Faults, Parasitic Extraction Method, layout fault model
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